Logic families

Results: 529



#Item
51AN408: Termination Options for Any-Frequency, Any-Output Clock Generators and Clock Buffers

AN408: Termination Options for Any-Frequency, Any-Output Clock Generators and Clock Buffers

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Source URL: www.silabs.com

Language: English - Date: 2013-10-10 18:24:12
52Daily Highlights RFIC Panel Session: Fabless design: got any problem with that? Time: Room: TCC Ballroom A  IMS Plenary Session:

Daily Highlights RFIC Panel Session: Fabless design: got any problem with that? Time: Room: TCC Ballroom A IMS Plenary Session:

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Source URL: www.ims2014.org

Language: English - Date: 2014-05-13 09:47:30
53WORKSHOPS AND SHORT COURSES Duration: 14:20 to 18:10 RoomWS03

WORKSHOPS AND SHORT COURSES Duration: 14:20 to 18:10 RoomWS03

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Source URL: www.eumweek.com

Language: English - Date: 2015-04-07 10:24:21
54July 2014 Vol. 21, No. 3 ISSN: Table of

July 2014 Vol. 21, No. 3 ISSN: Table of

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Source URL: eds.ieee.org

Language: English - Date: 2014-07-15 10:49:27
55Future Technology Devices International Ltd  TTL-232RG TTL to USB Serial Converter Generic Cables Datasheet

Future Technology Devices International Ltd TTL-232RG TTL to USB Serial Converter Generic Cables Datasheet

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Source URL: www.ftdichip.com

Language: English - Date: 2012-05-14 07:24:32
56CALL FOR PAPERS 2015 BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING Short Course: Monday, October 26, 2015 Conference: Tuesday, October 27- Wednesday, October 28, 2015 Hyatt Boston Harbor, MA, USA

CALL FOR PAPERS 2015 BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING Short Course: Monday, October 26, 2015 Conference: Tuesday, October 27- Wednesday, October 28, 2015 Hyatt Boston Harbor, MA, USA

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Source URL: www.ieee-bctm.org

Language: English - Date: 2015-01-27 17:21:28
57Self-timed circuitry for global clocking Scott Fairbanks Cambridge University  Abstract We present an apparatus used to distribute a timing reference or clock across the extent of a digital sy

Self-timed circuitry for global clocking Scott Fairbanks Cambridge University Abstract We present an apparatus used to distribute a timing reference or clock across the extent of a digital sy

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Source URL: www.cl.cam.ac.uk

Language: English - Date: 2005-12-06 10:52:57
58June 11, 2012  Tohoku University NEC Corporation  The World’s Smallest Cell Implementation for a High-Density

June 11, 2012 Tohoku University NEC Corporation The World’s Smallest Cell Implementation for a High-Density

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Source URL: www.csis.tohoku.ac.jp

Language: English - Date: 2012-06-07 22:51:21
59FAMILIES NSW: RESULTS LOGIC DIAGRAM A map of what we do according to the results that we are aiming to achieve for children, families and the community Results hierarchy  Children, families and communities are healthier,

FAMILIES NSW: RESULTS LOGIC DIAGRAM A map of what we do according to the results that we are aiming to achieve for children, families and the community Results hierarchy Children, families and communities are healthier,

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Source URL: www.families.nsw.gov.au

Language: English - Date: 2011-09-22 01:47:58
60EIAJ ED-5006A Standard of Japan Electronics & Information Technology Industries Association 1.0V±0.1V (normal range) and 0.7V to 1.1V(wide range) Power supply voltage and interface standard for non-terminated digital in

EIAJ ED-5006A Standard of Japan Electronics & Information Technology Industries Association 1.0V±0.1V (normal range) and 0.7V to 1.1V(wide range) Power supply voltage and interface standard for non-terminated digital in

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Source URL: home.jeita.or.jp

Language: English - Date: 2010-03-15 11:00:00